FMC ADC 100M 14B 4CHA

The FMC ADC 100M 14B 4CHA is a 4 channel 100 MSPS (Mega Sample Per Second) 14-bit ADC card in FMC format (FPGA Mezzanine Card).

The FMC ADC 100M 14B 4CHA uses by default only signals from the LPC rows of the HPC connector that is mounted. The gain can be set by software in three steps: ±50mV, ±0.5V, ±5V. An advanced offset circuit is used in the front-end design of the ADC board and allows a voltage shift in the range of ±5V that is independent of the chosen gain range.

• VITA 57.1-2010 compliance
• Bit/sample 14 bit
• sample rate of 105 MSPS (default 100MSPS)
• Analog bandwidth 30 MHz, DC-coupled (40 MHz possible by changing eight capacitors).
• Gain steps +/-50mV, +/-0.5V, +/-5V
• gain error of ±1%
• Offset correction range +/- 5V
• ENOB: 11.0, 11.5, 11.7 bit (at ±50mV, ±0.5V, ±5V range)
• SNR: 67.7 dB, 70.8 dB, 72.2 dB (at ±50mV, ±0.5V, ±5V range)
• 4 ADC channels, 4 LEMO 00 connectors for signals and one LEMO 00 connector for trigger
• 2 pairs serial LVDS for each channel
• Input impedance of 1 kΩ / 50 Ohm – software selectable
• FMC to carrier interface: FMC high pin count connector (HPC only used if external clock is selected)
• Clock source: internal from programmable on- board oscillator or external from dedicated FMC connector pins (HPC) when changing two capacitors.

This module can be used together with one of our Carriers for building control and measurement systems in MTCA standard. In particular, it is tailored to the requirements of fast hard real time systems with multi-channel processing and White Rabbit ultra-precise time synchronization. Use cases include control systems for large research infrastructures.

More technical information: https://ohwr.org/project/fmc-adc-100m14b4cha/wikis/home

We offer electronics engineering consultancy services, including: custom modifications of hardware, custom firmware and gateware modifications, system design, integration and testing.