FMC DAC 600M 12B 1CHA DDS

The FMC DAC 600M 12B 1CHA DDS is a FPGA Mezzanine Card module. It can be used to distribute RF signals over the White Rabbit network.

Together with the Simple PCIe FMC Carrier – SPEC, the FMC DAC 600M 12B 1CHA DDS board makes a complete WR RF distribution node. The idea of RF distribution over WR is described in the Distributed Direct Digital Synthesis over White Rabbit (D3S) project: https://ohwr.org/project/wr-d3s/wikis/home

Specifications

• Low-Pin Count FMC
• 14-bit 600MHz DAC (MAX5890EGK+D) with splitter and amplifier
• ADF4002 phase detector + programmable LPF + 16-bit ADC
• AD9510 PLL with external oscillator for jitter cleaning of the synthesized RF signal
• 4-layer PCB
• On-board thermometer IC (DS18B20U+)
• 64kbit EEPROM (24AA64T-I/MC) connected for storing application parameters
• 2 LEDs

I/Os (LEMO 00)

• 50 Ohm RF reference in (up to 500 MHz)
• 50 Ohm RF monitor/synthesis out (up to 500 MHz)
• Jitter < 20ps RMS (V2-1 design)
• Divided beam clock output (LVTTL)
• External Trigger input (LVTTL)
• Fine-delay adjusted RF synchronous trigger output (LVTTL)

Clocking resources

• 1x user-specified frequency VCTCXO controlled by the AD9510 PLL for low additional jitter cleaning
• 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
• Low-jitter frequency synthesizer/fanout (AD9516)
• Trigger output (beam-clock synchronous) with fine delay adjustment by SY89295

This module has been designed to be used together with the Simple PCIe FMC Carrier – SPEC for distributing periodic (mainly clock) signals of arbitrary frequencies over a White Rabbit network. Possible applications in the accelerators are: beam-synchronous timing, RF clock distribution and RF or beam-synchronous signal acquisition.

More technical information:

• https://ohwr.org/project/wr-d3s/wikis/home
• https://www.ohwr.org/projects/fmc-dac-600m-12b-1cha-dds/wiki

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