On the PCIe side it has a 4-lane interface, while the FMC mezzanine slot uses a low-pin count connector. This board is optimized for cost and is usable with most of the FMC cards designed within the OHWR project (e.g. ADC cards, Fine Delay).
- Xilinx Spartan6 FPGA (XC6SLX45T-3FGG484C)
- 256MB DDR3 2Gbit (MT41J128M16HA-15E)
- 32 MB SPI Flash for FPGA configuration (M25P32-VMF6P – EOL).
- 1x SFP cage for fiber optic transceiver (WR support) 1.25 and 2.5Gbps
- 2x SATA connector
- 1x JTAG header for Xilinx programming during debugging
- 1x Mini USB UART bridge
- Power connector jack 5.5/2.1mm
- 1×10-280 MHz I2C Programmable XO Oscillator, starts up at 100 MHz (Silicon Labs Si570, freely usable)
- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- 1x low-jitter frequency synthesizer (TI CDCM61004, fixed configuration, Fout=125 MHz, used by White Rabbit PTP core)
- Power supply 12V,
- Power consumption 5-12W
- 4-lane PCIe (Gennum GN4124)
- FMC slot with low pin count (LPC) connector
- on-board thermometer IC (DS18B20U+)
- unique 64-bit identifier (DS18B20U+)
- programmable Red and Green LEDs
- 2 buttons
- 6-layer PCB
This PCIe Carrier has been designed to be used together with a single FMC card and an SFP connector to build various elements of accelerator control systems. Use cases include large pixel detector readout systems, acquisition of bunch-by-bunch data streams and online processing of data applications using GPUs. The SPEC has been tested with links running up to 2.5Gbps allowing multiple data streams multiplexed onto a single link. SPEC is tailored to the needs of White Rabbit time and event distribution networks and can be implemented as a simple White Rabbit node in pair with FMC DIO 5CH TTL A.
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