Functional specifications |
Front Panel:
● 5 SMC connectors (1-PPS input and output, 62.5 MHz output, 10 MHz input)
● 18 cages for Gigabit SFP transceivers (connected to Xilinx GTXs)
● 10/100 Ethernet management port (connected to ARM CPU)
● Mini-USB UART management port (connected to ARM CPU)
● Power and Status LEDs
● Link and Act LEDs for each SFP cage
Back Panel:
● 2x Mini-USB UART debugging port (connected to ARM CPU and FPGA I/O pins)
● 2x cooling fan
● 2x microswitch, power button
● 1x grounding connector
Programmable resources:
● Xilinx Virtex-6 FPGA (LX240T FFG1156)
● ARM Atmel AT91 SAM9G45 CPU – 400MHz
Clocking resources:
● 1x Low-Jitter Clock Generator (Synthesizer 28-683MHz TI CDCM61002, used as DMTD offset clock in WR Switch HDL)
● 1x 25MHz VCXO, FRETHE025 controlled by DAC with SPI interface (AD5662 16bit 2.7-5.54V, used to drive CDCM61002 generator)
● 1x 25MHz VCO controlled by DAC with SPI interface (AD5662 16bit 2.7-5.54V, used to drive AD9516 generator)
● 1x 25MHz XO oscillator FNETHE025 (main FPGA clock)
● PLL – 14 Output Clock Generator with Integrated 1.6 GHz VCO (AD9516, clock signals for Xilinx GTXs, uTCA connectors)
● 1x Internal Oscillator (VM53S3-25.000, tuned to follow WR master clock or followed in Free Running mode)
Memory:
● 64MB DDR2
● 256MB NAND
● 8MB boot flash
Software:
● Linux – kernel v2.6.39
● Timing – WRP daemon (node discovery, etc.) PTPv2 daemon
Switching:
● 1x protocols (multicasting, spanning tree, GMRP/-GARP)
● VLAN Tagging
● SNMP switch management
Other:
● Protocols: TCP/IP, SSH, SNMP, TFTP, DHCP, ARP, DNS
● 1x FPGA JTAG connector
● 1x ARM JTAG connector
● 2x I2C multiplexer (PCA9548A)
● 1x I2C GPIO driver (PCA9554PW, driving Power and Status LEDs on the front panel)
● 9x I2C GPIO driver (PCA9554PW, driving LEDs for each SFP cage)
● Power supply 100-240VAC, 2.0A, 50-60Hz input, 12VDC, 6.66A, 80W output
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